1. Field of the Invention
The present invention relates to data processing that performs processing of 2-dimensionally arranged parameter information without damaging the arrangement rules by correlating image data to respective pixel locations. The present invention more particularly relates to a method of performing processing of all of the pixels of an area within image data without damaging the arrangement rules of 2-dimensional parameters even when the number of lines included in a unit of image processing (band) within the image data and the number of lines of 2-dimensional parameter information are not in agreement.
2. Description of the Related Art
Processing that correlates parameters, for which a positional relationship with each other has been set, with a plurality of data, for which the position relationship with each other has also been set, is used in various situations. For example, in image processing that generates data for an image to be printed by a printing apparatus, there is processing that correlates a binary dot pattern with the multi-value data of the individual pixels. Moreover, there is also processing for multi-pass printing that sets the dots that will actually be printed in each scan by correlating a mask pattern, for which the dots that are allowed and not allowed to be printed are set in advance, to dot patterns of individual pixels that are generated in this way.
When this kind of dot pattern or mask pattern is set for an image area non-periodically when possible, there is a need for a memory that stores the plurality of parameters that correspond to respective pixel locations in the image area such that they are in a state of having a fixed positional relationship with each other, or in other words, such that they are stored two dimensionally. However, when a CPU that performs the image processing above performs processing while sequentially accessing the memory where this kind of a plurality of parameters is stored, much time is required for the processing, so that, in the case of a printing apparatus, the printing speed is reduced.
In order to improve such a drop in processing speed, a method is known by which a high-speed memory (cache memory) is provided in the circuit that executes the processing, and processing is executed after the data that is stored in the large-capacity memory above (low-speed memory) has been stored in the high-speed memory. As a result, it is possible to reduce the number of times that the low-speed memory is accessed, and thus it is possible to reduce the time needed for image processing without affecting the printing speed. However, when a 2-dimensional table that is prepared for the non-periodic arrangement above is too large, the cache memory that is prepared in the circuit, or in other words, the scale of the circuit becomes large, and thus the cost increases.
In this way, conventionally, when correlating parameters that were arranged non-periodically with individual data it was difficult to achieve both a suitable circuit scale and high-speed processing.
Therefore, in Japanese Patent Laid-Open No. 2002-269577 construction is disclosed wherein part of the parameters stored in the low-speed memory are read into the cache memory, and processing is performed in order with the area corresponding to the stored parameters as the processing unit. By employing the method disclosed in Japanese Patent Laid-Open No. 2002-269577, as long as there is small memory capacity capable of storing only a one-line parameter, for example, access and processing can be performed at higher speed than was possible conventionally, even when it is not possible to store a large amount of information at one time in the cache memory.
However, in this case, even though it is possible to suppress the capacity of the cache memory, in a circuit which requires setting the CPU for each unit of processing, it becomes necessary for the CPU to access the settings and image data for each line, which may lead to an increase in overhead.